The present invention relates to semiconductor device assemblies, and more particularly to techniques for analyzing and debugging circuitry as may be applied, for example, to a flip-chip bonded integrated circuit.
In recent years, the semiconductor industry has seen tremendous advances in technology which have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of tens (or even hundreds) of MAPS (millions of instructions per second) to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages which receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
In the past, the die and package were first attached and then the electrical connections from the die to the package were made by wire bonding. The wire bonding procedure is simple in concept. A thin (0.7 to 1.0 mil) wire is first bonded to the chip bonding pad and spanned to the inner lead of the package lead frame. The third action was to bond the wire to the inner lead. Lastly, the wire is clipped and the entire process repeated at the next bonding pad. While simple in concept and procedure, wire bonding was critical because of the precise wire placement and electrical contact requirements. In addition to accurate placement, each and every wire must make a good electrical contact at both ends, span between the pad and the inner lead in a prescribed loop without kinks, and be at a safe distance from neighboring lead wires.
To increase the number of pad sites available for a die and to address other problems, a different chip packaging technique called controlled collapse chip connection or flip chip packaging is being adopted. In this technology, the bonding pads are provided with metal (solder) bumps. The bonding pads need not be on the periphery of the die and hence are moved to the site nearest the transistors and other circuit devices formed in the die. As a result, the electrical path to the pad is shorter. Electrical connection to the package is made when the die is flipped over the package with corresponding bonding pads and soldered. As a result, the dies are commonly called flip chips in the industry. Each bump connects to a corresponding package inner lead. The packages that result are lower profile and have lower electrical resistance and a shortened electrical path. The output terminals of the package may be ball-shaped conductive bump contacts (usually solder, or other similar conductive material) are typically disposed in a rectangular array. These packages are occasionally referred to as xe2x80x9cBall Grid Arrayxe2x80x9d (BAG). Alternatively, the output terminals of the package may be pins, and such a package is commonly known as pin grid array (PA) package.
Once the die is attached to the package, the backside portion of the die remains exposed. The transistors and other circuitry are generally formed in a very thin epitaxially grown silicon layer on a single crystal silicon wafer of which the die is singulated from. In a structural variation, a layer of insulating silicon dioxide is formed on one surface of a single crystal silicon wafer followed by the thin epitaxially grown silicon layer containing the transistors and other circuitry. This wafer structure is termed xe2x80x9csilicon on insulatorxe2x80x9d (SOI) and the silicon dioxide layer is called the buried oxide layer (BOX). The transistors formed on the SOI structure show decreased drain capacitance, resulting in a faster switch transistor.
The side of the die including the epitaxial layer containing the transistors and the other active circuitry is often referred to as the circuit side of the die or front side of the die. The circuit side of the die is positioned very near the package. The circuit side opposes the backside of the die. Between the backside and the circuit side of the die is single crystalline silicon and, in the case of SOI circuits, also a buried oxide layer. The positioning of the circuit side provides many of the advantages of the flip chip.
However, in some instances the orientation of the die with the circuit side face down on a substrate may be a disadvantage or present new challenges. When a circuit fails, when circuit testing is desired, or when it is necessary to modify a particular chip, access to the transistors and circuitry near the circuit side is obtained only from the back side of the chip. This is challenging for SOI circuits since the transistors are in a very thin layer (about 10 micrometers) of silicon covered by the buried oxide layer (less than about 1 micrometer) and the bulk silicon (greater than 500 micrometers). Thus, the circuit side of the SOI flip chip die is not visible or accessible for viewing using optical or scanning electron microscopy.
Although the circuit of the SOI integrated circuit (IC) is buried under the bulk silicon, infrared (IR) microscopy is capable of imaging the circuit because silicon is relatively transparent in these wavelengths of the radiation. However, because of the absorption losses of IR radiation in silicon, it is generally required to thin the die to less than 100 microns in order to view the circuit using IR microscopy. On a die that is 725 microns thick, this means removing at least 625 microns of silicon before IR microscopy can be used. Thinning the die for failure analysis of a flip chip bonded IC is usually accomplished in two or three steps. First, the die is thinned across the whole die surface. This is also referred to as global thinning. Global thinning is done to allow viewing of the active circuit from the backside of the die using IR microscopy. Mechanical polishing is one method for global thinning.
Once an area is identified as an area of interest and it is determined that access is needed to a particular area of the circuit, local thinning techniques can be used to thin an area smaller than the die size. Laser microchemical etching of silicon is one method of local thinning.
Sometimes it is necessary for failure analysis, or for design debug, after global and/or local thinning, to make electrical contact and probe certain nodes in the circuit. This testing can be performed via the thinned backside or via pads on the circuit side of the SOI chip. When testing via pads on the circuit side of the chip, the SOI chip is typically placed in a test fixture having a circuit connector arranged to connect to these circuit-side pads. The SOI chip is activated through the test fixture, and signals at the nodes are analyzed. For certain applications, it has been discovered in connection with the present invention that the above-described thinning to remove substrate material results in the circuitry over-heating. When there is insufficient substrate material for drawing heat away from the internal circuitry, for example, when the circuitry is running at high speeds, the internal circuitry overheats and becomes inoperative. Consequently, the analysis/debug efforts are defeated.
Accordingly, there is a need for a testing approach that overcomes the abovementioned shortcomings.
According to one aspect of the disclosure, the present invention provides an approach for testing a flip chip SOI semiconductor device after the backside of the chip has been thinned to expose a selected region in the substrate. Thinning removes substrate material useful for drawing heat away from the internal circuitry when the circuitry is running at high speeds. To compensate for this material loss, a test fixture having a passive, corrosion-resistant heat-dissipating device is arranged to draw heat from the backside of the device.
In one example embodiment, the present invention is directed to a method for testing a SOI semiconductor device having a circuit side and a backside. The method includes: thinning the SOI semiconductor device and exposing a selected region in the SOI semiconductor device at its back side; securing the SOI semiconductor device in a test fixture and arranging the SOI semiconductor for testing via its circuit side; and activating the SOI semiconductor device while using the passive, corrosion-resistant heat-conductive element to dissipate heat generated by the SOI semiconductor device.
In another example embodiment, the present invention is directed to an arrangement for testing a SOI semiconductor device having a circuit side and a backside. The test arrangement comprises: a test fixture adapted to secure the SOI semiconductor device; a passive, corrosion-resistant heat sink coupled to the SOI semiconductor device and adapted to conduct heat generated by the SOI semiconductor device. The test fixture is adapted to test the SOI semiconductor device while the SOI semiconductor device is activated and while the passive, corrosion-resistant heat sink dissipates heat generated by the SOI semiconductor device. In a more particular embodiment, the SOI semiconductor device includes a circuit die and a package, with the passive, corrosion-resistant heat sink coupled to the package and drawing heat from the device through the package.
The above summary is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and the detailed description, which follow more particularly, exemplify these embodiments.